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Designing Semiconductor Solutions for Automotive Embedded Control Systems
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QualityThe semiconductor industry's outgoing quality level of integrated circuits has steadily improved over the last 25 years. Quality levels have gone from parts per thousands to today's standard of parts per million. At the same time, circuit complexity has increased from hundreds of transistors to millions of transistors. Although significant advancements have been made, AIEC continuously strives to improve on existing quality levels. For example, AIEC implements several methods for quality improvement including design for testability, Built In Self Test (BIST), 99% fault coverage, IDDQ testing, robust product design, and design reusability. Some of the details surrounding AIEC's continuous improvement quality control programs are outlined below. Please do not hesitate to contact us if you have specific requirements or concerns with regards to the quality plan. Quality StatementAIEC's commitment to quality is to provide products and services that meet or exceed its customers' expectations in the following areas:
Quality Plan (QS-9000 Compliant)As a "Design Responsible Supplier", AIEC is exempt from the requirements of QS-9000 and the associated certification. However, AIEC derives its quality plan per the Quality Systems Requirements (QS-9000) including the ISO 9000-Based Requirements and Customer-Specific Requirements. ISO 9000-Based RequirementsAIEC uses several tools to comply with the ISO 9000 based requirements, mainly:
Advanced Product Quality Planning (APQP)The Advanced Product Quality Plan (APQP) is used as a structured method for defining and establishing the steps necessary to assure customer satisfaction for AIEC's products and services. AIEC generates a unique APQP document for each Integrated Circuit (IC) design. The structure of the document closely parallels the following figure, which depicts the five phases of the product quality planning.
Design Failure Mode and Effects Analysis (DFMEA)The Potential Failure Mode and Effects Analysis manual defines DFMEA as an analytical technique used primarily by a Design-Responsible Engineer/Team as a means to ensure that, to the extent possible, potential failure modes and their associated causes/mechanisms have been considered and addressed. AIEC extensively uses DFMEA for each IC design that it undertakes. Stress Test Qualification for Integrated Circuits (AEC-Q100)The Automotive Electronics Council publishes a document entitled Stress Test Qualification for Integrated Circuits (AEC-Q100). AIEC uses this document extensively as part of its validation process. Specifically, AIEC meets or exceeds all the requirements of the attachment number 7, entitled Fault Simulation and Test Grading. Production Part Approval Process (PPAP)AIEC works closely with the semiconductor suppliers in preparation for submitting the Production Part Approval Process (PPAP) package. In fact, AIEC provides the supplier with all aspects of the design documentation including design records, engineering change documentation, and DFMEA documentation in the QS-9000 approved format. Customer-Specific RequirementsAIEC's commitment to quality focuses on meeting or exceeding customer expectations. As a result, AIEC has the flexibility to add customer specific requirements to its existing quality plan. Quality LinksDocumentation with regards to QS-9000, APQP, DFMEA, and PPAP can be ordered from the Automotive Industry Action Group from the following web page:http://www.aiag.org/publications/quality/dcxfordgm.asp The specification Stress Test Qualification for Integrated Circuits (AEC-Q100), can be downloaded from the following web page: QS-9000 is generally recognized in North America as the automotive quality systems requirements standard. The ISO/TS 16949 is the emerging worldwide quality systems requirements standard. Additional information on the ISO/TS 16949 standard can be found on the following web page: |